S.No |
Reg No |
Topic |
1 |
1 |
Transient Analysis of a CMOS Inverter
Driving Resistive Interconnect |
2 |
2 |
Master-Slave TMR Inspired Technique for
Fault Tolerance of SRAM-based FPGA |
3 |
3 |
Communications via systems on chips
clustering in large scaled sensored networks |
4 |
4 |
Design and comparison of low power and high
speed 4bit ALU |
5 |
5 |
Two new low power high performance full
address with minimum gates |
6 |
6 |
SOC synthesis with automatic hard ware
software interface generation |
7 |
7 |
On chip multi channel waveform monitoring
for diagnostics of mixed signal VLSI subjects |
8 |
8 |
Leakage temperature dependency modeling in
system level analysis |
9 |
9 |
Low power tunable analog circuit blocks
based on |
10 |
10 |
Statistical design optimization of F in FET
SRAM using back gate voltage |
11 |
11 |
Integration and implementation of secured IP
based Surveillance networks |
12 |
12 |
Memory less pipeline dynamic circuit design
technique |
13 |
13 |
Compressive acquisition CMOS image sensor
from the algorithm to hardware
implementation |
14 |
14 |
Decoding in analog VLSI |
15 |
15 |
The improved data encryption standard(DES)
algorithm |
16 |
16 |
A new VLSI architecture of parallel
multiplier – accumulator based on radix to
modified booth algorithm |
17 |
10102304 |
Highly Parallel FPGA emulation for
LPDC error floor
characterization in perpendicular magnetic
recording channel |
18 |
10102308 |
Vector bank based multimedia CODECSOC design |
19 |
10102312 |
MOORE's LAW PAST 32nm:future challenges in
DEVICE SCALING |
20 |
10102298 |
Communications via SOC Cluttering in large
scaled sensor networks |
21 |
10102302 |
Pattern based interactive method for extreme
large power/grand analysis |
22 |
10102328 |
Double sampling architecture for performing
fine time interpolation with in a limited logic
FPGA |
23 |
10102310 |
FPGA interpolation for humidity and
temperature remote sensing systems |
24 |
10102306 |
VHDL modeling of Wi-Fi MAC layer to
transmitter |
25 |
10102323 |
VLSI on chip power/grand network
optimization considering decap leakage currents |
26 |
10102334 |
temperature control frame work using
wireless sensor networks and acoustical analysis
for total special awareness |
27 |
10102313 |
Data rendition flip-flops for
power down applications |
28 |
10102321 |
On chip ESD protection sgategics for RF
circuits in CMOS technologies |
29 |
10102332 |
Trend and challenge on SOC design |
30 |
10102301 |
An anti harmonic programmable DLL-based
Frequency multiplier for dynamic
frequency scaling |
31 |
10102308 |
Intrusion aware SOC design which uncertainty
classifications |
32 |
10102303 |
Bio chip future basis for DNA computers |
33 |
10102315 |
Master-Slave TNR inspired
technique for fault tolerance at SRAM based FPGA |
34 |
10102322 |
Low cost MIMO testing for RF integrated
circuits |
35 |
10102318 |
Design and comparison of Low power and high
speed 4-bit ALU |
36 |
10102298 |
Simulation of power grid networks
considering wires and lognormal leakage current
variations |
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